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? semiconductor MSM5716C50/msm5718c50/md5764802 1/45 ? semiconductor MSM5716C50/msm5718c50/ md5764802 16m/18mb (2m 8/9) & 64mb (8m 8) concurrent rdram description the 16/18/64-megabit concurrent rambus? drams (rdram?) are extremely high-speed cmos drams organized as 2m or 8m words by 8 or 9 bits. they are capable of bursting unlimited lengths of data at 1.67 ns per byte (13.3 ns per eight bytes). the use of rambus signaling level (rsl) technology permits 600 mhz transfer rates while using conventional system and board design methodologies. low effective latency is attained by operating the two or four 2kb sense amplifiers as high speed caches, and by using random access mode (page mode) to facilitate large block transfers. concurrent (simultaneous) bank operations permit high effective bandwidth using interleaved transactions. rdrams are general purpose high-performance memory devices suitable for use in a broad range of applications including pc and consumer main memory, graphics, video, and any other application where high-performance at low cost is required. features ? compatible with base/ll rdrams ? 600 mb/s peak transfer rate per rdram ? rambus signaling level (rsl) interface ? synchronous, concurrent protocol for block-oriented, interleaved (overlapped) transfers ? 480 mb/s effective bandwidth for random 32 byte transfers from one rdram ? 13 active signals require just 32 total pins on the controller interface (including power) ? 3.3 v operation ? additional/multiple rambus channels each provide an additional 600 mb/s bandwidth ? two or four 2kbyte sense amplifiers may be operated as caches for low latency access ? random access mode enables any burst order at full bandwidth within a page ? graphics features include write-per-bit and mask-per-bit operations ? available in horizontal surface mount plastic package (shp32-p-1125-0.65-k) preliminary e2g1059-18-63 this version: jun. 1998 previous version: oct. 1997
? semiconductor MSM5716C50/msm5718c50/md5764802 2/45 part numbers the 16/18- and 64-megabit rdrams are available in horizontal surface mount plastic package (shp), with 533 and 600 mhz clock rate. the part numbers for the various options are shown in table 1. table 1 part numbers by option 533 mhz options 16-megabit shp MSM5716C50-53gs-k 600 mhz MSM5716C50-60gs-k 18-megabit shp msm5718c50-53gs-k msm5718c50-60gs-k 64-megabit shp md5764802-53gs-k md5764802-60gs-k
? semiconductor MSM5716C50/msm5718c50/md5764802 3/45 rdram packages and pinouts rdrams are available in horizontal surface mount plastic package (shp). the package has 32 signal pins and four mechanical pins that provide support for the device. the mechanical pins are located on the opposite side from the signal leads in the shp. vdd 1 gnd 2 dq8 3 gnd 4 dq7 5 nc (16/18m) ; vref (64m) 6 address 7 vdd 8 dq6 9 gnd 10 dq5 11 vdda 12 rxclk 13 gnda 14 txclk 15 vdd 16 dq4 17 gnd 18 command 19 sin 20 vref 21 sout 22 dq3 23 gnd 24 dq2 25 (nc) 26 dq1 27 gnd 28 dq0 29 (nc) 30 gnd 31 vdd 32 fig. 1 shp pin numbering
? semiconductor MSM5716C50/msm5718c50/md5764802 4/45 table 2 pin descriptions signal lines for req, din, and dout packets. the req packet contains the address field, command field, and other control fields. these are rsl signals. a signal i/o description dq8..dq0 (busdata [8:0]) i/o receive clock. all input packets are aligned to this clock. this is an rsl signal. a clk (rxclk) i transmit clock. dout packets are aligned with this clock. this is an rsl signal. a clk (txclk) i logic threshold reference voltage for rsl signals. vref i signal line for req, rstrb, rterm, wstrb, wterm, reset, and cke packets. this is an rsl signal. a command (busctrl) i signal line for col packets with column addresses. this is an rsl signal. a address (busenable) i +3.3 v power supply. vdda is a separate analog supply for clock generation in the rdram. vdd, vdda circuit ground. gnda is a separate analog ground for clock generation in the rdram. gnd, gnda initialization daisy chain input. cmos levels. sin i initialization daisy chain output. cmos levels. sout o a. rsl stands for rambus signaling levels, a low-voltage-swing, active-low signaling technology. pin 1 pin 32 mechanical support pins mechanical support pins fig. 2 shp package
? semiconductor MSM5716C50/msm5718c50/md5764802 5/45 general description figure 3 is a block diagram of an rdram. at the bottom is a standard dram core organized as two or four independent banks, with each bank organized as 512 or 1024 rows, and with each row consisting of 2kbytes of memory cells. one row of a bank may be activated at any time (actv command) and placed in the 2kbyte page for the bank. column accesses (read and write commands) may be made to this active page. the smallest block of memory that may be accessed with read and write commands is an octbyte (eight bytes). bitmask and bytemask options are available with the write command to allow finer write granularity. there are six control registers that are accessed at initialization time to configure the rdram for a particular application.
? semiconductor MSM5716C50/msm5718c50/md5764802 6/45 initialize/powerdown 1:8 demux 8:1 mux din 64/72 dout 72 64/72 64/72 sin 11 sout 1 1 rxclk 1 1 address (busenable) 1 1 command (busctrl) dq8, dq7,...dq0 (busdata[8:0]) 99 91 1 txclk 88 devicetype register deviceid register mode register refrow register rasinterval register devicemfgr register control logic req rstrb, rterm wstrb, wterm cke, reset mask register 64/72 d 64/72 256 page 64/72 256 64/72 256 1024 bank 3 c 64/72 d 64/72 256 a page 64/72 256 a 64/72 256 a 512 b bank 1 64/72 d 64/72 256 page 64/72 256 64/72 256 1024 bank 2 c 64/72 d 64/72 256 a page 64/72 256 a 64/72 256 a 512 b bank 0 c 4 banks per rdram for 64m 64/72 256 a 512 b bank 1 a 256 octbytes per row for 64m b 1024 rows per bank for 64m 64/72 256 a 512 b bank 0 a 256 octbytes per row for 16m/18m b 512 rows per bank for 16m/18m d64/72: 64b for 16m/64m 72b for 18m fig. 3 16/18/64-mbit concurrent rdram block diagram
? semiconductor MSM5716C50/msm5718c50/md5764802 7/45 fig. 4 read and write transaction examples basic operation figure 4 (a) shows an example of a read transaction. a transaction begins in interval t 0 with the transfer of a req packet. the req packet contains the command (actv/read), a device, bank, and row address (bnk/row) of the page to be activated, and the column address (cola) of the first octbyte to be read from the page. the selected bank performs the activation of the selected row during t 1 and t 2 (the t rcd interval). next, the selected bank reads the selected octbyte during t 3 and t 4 (the t cac interval). a second command rstrb (read strobe) is transferred during t 3 and causes the first octbyte (douta) to be transferred during t 5 . t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 clk (rx/txclk) address (busenable) command (busctrl) dq8,..dq0 (busdata[8:0]) bank operation col b col c col d rstrb rterm dout a dout b dout c dout d actv /read req packet next req bnk/row /col a t rcd t cac (a) bank activate and random read cycles within a page t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 clk (rx/txclk) address (busenable) command (busctrl) dq8,..dq0 (busdata[8:0]) bank operation col b col c col d wstrb wterm din a din b din c din d actv /write req packet next req bnk/row /col a t rcd (b) bank activate and random write cycles within a page
? semiconductor MSM5716C50/msm5718c50/md5764802 8/45 in this example, three additional octbytes are read from the activated page. these column addresses (colb, colc, and cold) are transferred in t 3 , t 4 , and t 5 , respectively. the data octbytes (doutb, doutc, and doutd) are transferred in t 5 , t 6 , and t 7 , the end of the data octbytes is signaled by a third command rterm (read terminate) in t 6 . the next req packet may be sent in t 9 , or in any interval thereafter. figure 4 (b) shows an example of a write transaction. the transaction begins in interval t 0 with the transfer of a req packet. the req packet contains, the command (actv/write), a device, bank, and row address (bnk/row) of the page to be activated, and the column address (cola) of the first octbyte to be written to the page. the selected bank performs the activation of the selected row during t 1 and t 2 (the t rcd interval). a second command wstrb (write strobe) is transferred during t 2 and causes the first octbyte (dina) to be transferred during t 3 . in this example, three additional octbytes are written to the activated page. these column addresses (colb, colc, and cold) are transferred in t 2 , t 3 , and t 4 respectively. the data octbytes (dinb, dinc, and dind) are transferred in t 4 , t 5 , and t 6 . the end of the data octbytes is signaled by a third command wterm (write termination) in t 6 . the next req packet may be sent in t 7 , or in any interval thereafter. interleaved transactions the previous examples showed noninterleaved transactions - the next req packet was transferred after the last data octbyte of the current transaction. in an interleaved transaction, the next req packet is transferred before the first data octbyte of the current transaction. this permits the row and column access intervals of the next transaction to overlap the data transfer of the current transaction. figure 5 shows an example of interleaved read transactions. the first transaction proceeds exactly as the noninterleaved example of figure 4 (a) (all packets of the first transaction are labeled with 1). however, in t 5 the req packet for the second transaction is transferred (all packets of the second transaction are labeled with 2). the t rcd2 and t cac2 intervals overlap the transfer of dout1 data octbytes and thus increase the effective bandwidth of the rdram since there are no unused intervals. a transaction consists of an address transfer phase and a data transfer phase. the req packet performs address transfer, and the remaining packets perform data transfer (dout, col, rstrb, and rterm in the case of a read transaction). the time interval between the address and data transfer phases of the current transaction may be adjusted to match the data length of the previous transaction (as long as the row and column access times for the current transaction are observed). thus, there are no limits on the types of memory transaction which may be interleaved; any mixing of transaction length and command type is permitted.
? semiconductor MSM5716C50/msm5718c50/md5764802 9/45 t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 clk (rx/txclk) address (busenable) command (busctrl) dq8,..dq0 (busdata[8:0]) bank operation col c0 col d0 col b1 rterm1 rstrb1 dout a0 dout b0 dout c0 dout d0 actv /read req packet 1 bnk/row /col a1 t rcd1 t cac1 col c1 col d1 col b2 col c2 actv /read req packet 2 bnk/row /col a2 rterm2 rstrb2 dout a1 dout b1 dout c1 dout d1 t rcd2 t cac2 actv /read req packet 3 bnk/row /col a3 data transport 0 overlaps row/column access 1 data transport 1 overlaps row/column access 2 fig. 5 interleaved read transaction example
? semiconductor MSM5716C50/msm5718c50/md5764802 10/45 req packet (address transfer) an req packet initiates a transaction by transferring the address and command information to the rdram. figure 6 shows the format of the req packet. note that each rdram wire carries eight bits of information in each t packet . this is the time required to transfer an octbyte of data and is the natural granularity with which to illustrate timing relationships. the clock that is actually used by the rdram has a period of t cycle , with information transferred on each clock edge. t packet is four times t cycle . in the req packet, the bits which are gray are reserved, and should be driven with a zero. in particular, the bits in t cycle t 6 and t 7 are needed for bus-turn-around during read transactions. a35..a3: the address field a35..a3 consumes the greatest number of bits. these are allocated to device, bank, row, and column addressing according to table 3: table 3 a35..a3 address fields op5..op0: the command field op5..op0 specifies the type of transaction that is to be performed, according to table 4. the op0 bit selects a read or write transaction, the op1 bit selects a memory or register space access, and op5..op2 select command options. these command options include b in op2 (see byte masking on page 22). d in op3 for selecting broadcast operations (see refresh on page 35), and b1, b0 in op5, op4 (see bit masking on page 23). actv: this bit specifies activation or precharge/activation of a bank at the beginning of a transaction, and is designated by prepending actv/ or pre/actv/ to the command. auto: this bit specifies auto-precharge of a bank at the end of the transaction, and is designated by appending a to the command. start: this bit is always set to a one and indicates the beginning of a request to the rdram. regsel: this bit is used for accessing registers. pend2...pend0: this field is set to 000 for noninterleaved transactions, and to a nonzero value for interleaved transactions. this is the number of previous strb and term packets the rdram is to skip. refer to the concurrent rdram design guide for further details. m7..m0: this field is used to perform byte masking of the first data octbyte dina for all memory write transactions (op1, op0 = 01). refer to byte masking on page 22. field 16m/18m (2kb page) col a10..a3 row a19..a11 bnk a20 dev a35..a21 64m (2kb page) a10..a3 a20..a11 a22, a21 a35..a23
? semiconductor MSM5716C50/msm5718c50/md5764802 11/45 table 4 command encoding actv auto op5 op4 op3 op2 op1 op0 command description 00000x00 read read 0 0 b1 b0 d b 0 1 write write (b1, b0, b masking and d broadcast options) 00000110 rreg register read 0000d111 wreg register write (d) 01000x00 reada read/autoprecharge 0 1 b1 b0 d b 0 1 writea write/autoprecharge (b1, b0, d, b) 10000x00 actv/read activate/read 1 0 b1 b0 d b 0 1 actv/write activate/write (b1, b0, d, b) 11000x00 actv/reada activate/read/autoprecharge 1 1 b1 b0 d b 0 1 actv/writea activate/write/autoprecharge (b1, b0, d, b) 10000x00 pre/actv/read precharge/activate/read 1 0 b1 b0 d b 0 1 pre/actv/write precharge/activate/write (b1, b0, d, b) 11000x00 pre/actv/reada precharge/activate/read/autoprecharge 1 1 b1 b0 d b 0 1 pre/actv/writea precharge/activate/write/autoprecharge (b1, b0, d, b)
? semiconductor MSM5716C50/msm5718c50/md5764802 12/45 fig. 6 req packet format op4 op2 op5 op1 start a35 a26 op3 op0 a34 a25 a17 a9 a33 a24 a16 a8 a32 a23 a15 a7 a31 a22 a14 a6 a30 a21 a13 a5 a29 a20 a12 a4 a27 a18 a10 regsel actv auto pend2 pend0 m7 m6 m5 m4 m3 m2 m0 a28 a19 a11 a3 command dq8 dq7 dq6 dq5 dq4 dq3 dq2 dq0 dq1 address clk pend1 m1 t 3 t 2 t 1 t 0 clk (rx/txclk) address (busenable) command (busctrl) dq8,..dq0 (busdata[8:0]) actv /read req packet bnk/row /col a t cycle t 0 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t packet t packet = 4 ? t cycle
? semiconductor MSM5716C50/msm5718c50/md5764802 13/45 data transfer packets the next set of packet types are used for data transfer. their formats are summarized in figure 7. as in the req packet, eight bits are transferred on each wire during each t packet interval. the rising and falling edges of the rdram clock define the transfer windows for each of these bits. the data transfer packets will align to the t packet intervals defined by the start bit of the req packet by simply observing the timing rules that are developed in the next few sections of this document. din and dout packets there are nine wires allocated for the data bytes. these wires are labeled dq8..dq0. the eight bytes transferred in a din or dout packet have 72 bits, which are labeled d0..d63 (on the dq0..dq7 wires) and e0..e7 (on the dq8 wire). the 18mbit rdram have storage cells for the e0..e7 bits. the e0..e7 bits are also used with byte masking operations. this is described in the section on byte masking on page 22. col packet the column address a10..a3 of the first octbyte of data (dina or douta) is provided in the req packet. the col packet contains an eight bit field a10..a3, which provides the column address for the second and subsequent data octbytes. the col packets have a fixed timing relationship with respect to the din and dout packets to which they correspond. as the din and dout packets are moved (to accommodate interleaving ). the col packets move with them. rstrb and rterm packets the rstrb and rterm packets indicate the beginning and end of the dout packets that are transferred during a read transaction. the rstrb and rterm packets are each eight bits and consist of a single 1 in an odd t cycle position, with the other seven positions 0. note that when a transaction transfers a single data octbyte, the rstrb and rterm packets will overlay one another. this is permitted and is in fact the reason that each packet consists of a single asserted bit. an example of this case is shown in figure 14 (a). there will be transaction situations in which the rterm overlays a req packet (two octbyte interleaved transaction). again, this is permitted. the general rule is that the rterm may overlay any of the other packets on the command (busctrl) wire, and rstrb may overlay any other except for a req packet. wstrb and wterm packets the wstrb and wterm packets indicate the beginning and end of the series of din packets that are transferred during a write transaction. the wstrb and wterm packets are each eight bits and consist of a single 1 in an odd t cycle position, with the other seven positions 0. note that when a transaction transfers a single data octbyte, the wstrb and wterm packets will not overlay one another (unlike the case of a one octbyte read). an example of this case is shown in figure 14 (b). there will be transaction situations in which the wstrb overlays a req packet (no bank activate). again, this is permitted. an example of this is shown in figure 9 (a). the general rule is that the wstrb may overlay any of the other packets on the command (busctrl) wire, and wterm may overlay any other except for a req packet.
? semiconductor MSM5716C50/msm5718c50/md5764802 14/45 cke packet the average power of the rdram can be reduced by using suspend power mode. this is done by setting the fr field of the mode register to a zero (the mode register is shown in figure 17). a cke packet must be sent a time t cke ahead of each req packet (this is shown in interval t 0 in figure 21 (b)). this causes the rdram to transition from suspend to enable mode. when the rdram has finished the transaction, it returns to suspend mode. the cke packet will overlay the rstrb and rterm packets when transactions are interleaved. if the fr field is set to a one, cke packets are not used and the rdram remains in enable mode. reset packet the reset packet is used during initialization. when reset packets are driven for a time t reset or greater, the rdram will assume a known state. because the reset packet is limited to this one use, it will not interact with the other packet types. this is illustrated in figure 21 (a). pwrup packet the pwrup packet is used to cause an rdram to transition from powerdown to enable mode. this is illustrated in figure 21 (c).
? semiconductor MSM5716C50/msm5718c50/md5764802 15/45 fig. 7 din, dout, col, cke, rstrb, rterm, wstrb, wterm, and reset packet formats e3 e2 e1 e0 d31 d23 d15 d7 d30 d22 d14 d6 d29 d21 d13 d5 d28 d20 d12 d4 d27 d19 d11 d3 d26 d18 d10 d2 d24 d16 d8 d0 d25 d17 d9 d1 dq8 dq7 dq6 dq5 dq4 dq3 dq2 dq0 dq1 address clk command command command command command command command t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 e7 e6 e5 e4 a6 a5 a4 a3 a10 a9 a8 a7 1 1 1 1 d63 d55 d47 d39 d62 d54 d46 d38 d61 d53 d45 d37 d60 d52 d44 d36 d59 d51 d43 d35 d58 d50 d42 d34 d57 d49 d41 d33 d56 d48 d40 d32 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 clk din a din b din c din d dout a dout b dout c dout d col b col c col d cke rterm wterm pwrup reset wstrb rstrb 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
? semiconductor MSM5716C50/msm5718c50/md5764802 16/45 read transactions when a controller issues a read request to an rdram, one of three transaction cases will occur. this is a function of the request address and the state of the rdram . read: the first case is shown in figure 8 (a). this occurs when the requested bank has been left in an activated state and the requested row address matches the address of this activated row. this is also called a page hit read and is invoked by the read or reada commands. there are three timing parameters which specify the positioning of the packets which control the data transfer. these are as follows: t sdr start of rstrb to start of dout t cdr start of col to start of dout t tdr start of rterm to end of dout these parameters are all expressed in units of t cycle , and the minimum and maximum values are the same; the rstrb, rterm, col, and dout packets move together as a block. a fourth parameter has a minimum value only, and positions the block of data transfer packets relative to the req (address transfer) packet: t rsr start of req to start of rstrb for read when a read transaction is formed, these packet constraints must be observed. in addition, there are constraints upon the timing of the bank operations which must also be observed. these are shown in figure 8 (a) next to the label bank operation. after the transfer of the req packet in t 0 , the rdram performs a column access (requiring t cac for the column access time) of the first data octbyte douta during t 1 and t 2 . the rdram performs three column cycles (requiring t cc for the column cycle time) in order to access the next three data octbytes (doutb. doutc, doutd) during t 3 , t 4 and t 5 . each data octbyte is transferred one t packet interval after it is accessed. actv/read: the second case is shown in figure 8 (b). this occurs when the requested bank has been left in a precharged state. this is invoked by the actv/read and actv/reada commands. the rstrb, rterm, col, and dout packets remain in the same relative positions as in the read case, but they move further from the req packet: t asr start of req to start of rstrb for actv/read after the transfer of the req packet in t 0 , the rdram performs an activation operation (requiring t rcd for the row-column delay) during t 1 and t 2 . this leaves the requested row activated. from this point the sequence of bank operations are identical to the read case, except that everything has shifted two t packet intervals further from the req packet. the sum of t rcd and t cac is also known as t rac (the row access time).
? semiconductor MSM5716C50/msm5718c50/md5764802 17/45 pre/actv/read: the third case is shown in figure 8 (c). this occurs when the requested bank has been left in an activated state and the requested row address doesnt match the address of this activated row. this is also called a page miss read and is invoked by the pre/actv/read and pre/actv/reada commands. the rdram knows the difference between a pre/actv/ read and a actv/read because each rdram bank has a flag indicating whether it is precharged or activated. the external controller tracks this flag, and also tracks the address of each activated bank in order to distinguish read and pre/actv/read accesses. the rstrb, rterm, col, and dout packets remain in the same relative positions as in the read case, but they move further from the req packet: t psr start of req to start of rstrb for pre/actv/read after the transfer of the req packet in t 0 , the rdram performs a precharge operation (t rp ) during t 1 and t 2 , and an activation operation (t rcd ) during t 3 and t 4 . this leaves the requested row activated. from this point the sequence of bank operations are identical to the read case, except that everything has shifted four t packet intervals further from the req packet. the sum of t rp , t rcd , and t cac is also known as t rc (the row cycle time). auto-precharge option: for a read, actv/read, or a pre/actv/read command, the bank operations are complete once the last data octbyte has been accessed. the bank will be left with the requested row activated. for a reada, actv/reada, or a pre/actv/reada command, there is an additional step. during the two t packet intervals after the last data octbyte access an auto- precharge operation (requiring t rpa for the row precharge, auto) is performed. this leaves the bank in a precharged state. t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 clk (rx/txclk) address (busenable) command (busctrl) dq8,..dq0 (busdata[8:0]) bank operation col b col c col d rterm dout a dout b dout c dout d reada req packet bnk /col a t cac (a) reada - random read cycles within a page t sdr t cdr t rsr t tdr t rpa t cc t cc t cc rstrb
? semiconductor MSM5716C50/msm5718c50/md5764802 18/45 t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 clk (rx/txclk) address (busenable) command (busctrl) dq8,..dq0 (busdata[8:0]) bank operation col b col c col d rstrb rterm dout a dout b dout c dout d actv /reada req packet bnk/row /col a t cac (b) actv/reada - bank activate and random read cycles within a page t sdr t cdr t asr t tdr t rpa t cc t cc t cc t rcd t rac t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 clk (rx/txclk) address (busenable) command (busctrl) dq8,..dq0 (busdata[8:0]) bank operation col b col c col d rstrb rterm dout a dout b dout c dout d pre/actv /reada req packet bnk/row /col a t cac (c) pre/actv/reada - bank precharge/activate and random read cycles in a page t sdr t cdr t psr t tdr t rpa t cc t cc t cc t rp t rcd t rc fig. 8 read transactions
? semiconductor MSM5716C50/msm5718c50/md5764802 19/45 write transactions when a controller issues a write request to an rdram, one of three transaction cases will occur. this is a function of the request address and the state of the rdram. write: the first case is shown in figure 9 (a). this occurs when the requested bank has been left in an activated state and the requested row address matches the address of this activated row. this is called a page hit write and is invoked by the write or writea commands. there are three timing parameters which specify the positioning of the packets which control the data transfer. these are as follows: t sdw start of wstrb to start of din t cdw start of col to start of din t tdw start of wterm to end of din these parameters are all expressed in units of t cycle , and the minimum and maximum values are the same; the wstrb, wterm, col, and din packets move together as a block. a fourth parameter has a minimum value only, and positions the block of data transfer packets relative to the req (address transfer) packet: t wsw start of req to start of wstrb for write when a write transaction is formed, these packet constraints must be observed. in addition, there are constraints upon the timing of the bank operations which must also be observed. these are shown in figure 9 (a) next to the label bank operation. after the transfer of the req packet in t 0 , the rdram performs a column access (requiring t cac for the column access time) of the first data octbyte dina during t 1 and t 2 , the rdram performs three column cycles (requiring t cc for the column cycle time) in order to access the next three data octbytes (dinb, dinc. dind) during t 3 , t 4 and t 5 . each data octbyte is transferred one t packet interval before it is accessed. actv/write: the second case is shown in figure 9 (b). this occurs when the requested bank has been left in a precharged state. this is invoked by the actv/write and actv/writea commands. the wstrb, wterm, col, and din packets remain in the same relative positions as in the page hit case, but they move further from the req packet: t asw start of req to start of wstrb for actv/write after the transfer of the req packet in t 0 , the rdram performs an activation operation (called t rcd or row-column delay) during t 1 and t 2 . this leaves the requested row activated. from this point the sequence of bank operations are identical to the write case, except that everything has shifted two t packet intervals further from the req packet. the sum of t rcd and t cac is also known as t rac (the row access time).
? semiconductor MSM5716C50/msm5718c50/md5764802 20/45 pre/actv/write: the third case is shown in figure 9 (c). this occurs when the requested bank has been left in an activated state and the requested row address doesnt match the address of this activated row. this is also called a page miss write and is invoked by the pre/actv/write and pre/actv/writea commands. the rdram knows the difference between a pre/actv/ write and a actv/write because each rdram bank has a flag indicating whether it is precharged or activated. the external controller tracks this flag, and also tracks the address of each activated bank in order to distinguish pre/actv/write and write accesses. the wstrb, wterm, col, and din packets remain in the same relative positions as in the write case, but they move further from the req packet: t psw start of req to start of wstrb for pre/actv/write after the transfer of the req packet in t 0 , the rdram performs a precharge operation (t rp ) during t 1 and t 2 , and an activation operation (t rcd ) of during t 3 and t 4 . this leaves the requested row activated. from this point the sequence of bank operations are identical to the write case, except that everything has shifted four t packet intervals further from the req packet. the sum of t rp , t rcd , and t cac is also known as t rc (the row cycle time). auto-precharge option: for a write, actv/write or a pre/actv/write command, the bank operations are complete once the last data octbyte has been accessed. the bank will be left with the requested row activated. for a writea, actv/writea or a pre/actv/writea command, there is an additional step. during the two t packet intervals after the last data octbyte access an auto- precharge operation (requiring t rpa for the row precharge, auto) is performed. this leaves the bank in a precharged state. t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 clk (rx/txclk) address (busenable) command (busctrl) dq8,..dq0 (busdata[8:0]) bank operation col b col c col d wterm din a din b din c din d wstrb writea req packet bnk/row /col a t cac (a) writea - random write cycles within a page t tdw t cdw t wsw t rpa t cc t cc t cc t sdw
? semiconductor MSM5716C50/msm5718c50/md5764802 21/45 t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 clk (rx/txclk) address (busenable) command (busctrl) dq8,..dq0 (busdata[8:0]) bank operation col b col c col d wterm din a din b din c din d actv /writea req packet bnk/row /col a t rcd (b) actv/writea - bank activate and random write cycles within a page t tdw t cdw t rpa t cc t cc t cc t sdw wstrb t cac t asw t rac t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 clk (rx/txclk) address (busenable) command (busctrl) dq8,..dq0 (busdata[8:0]) bank operation col b col c col d wterm din a din b din c din d actv /writea req packet bnk/row /col a t rcd (c) pre/actv/writea - bank precharge/activate and random write cycles in a page t tdw t cdw t rpa t cc t cc t cc t sdw wstrb t cac t psw t rc t rp fig. 9 write transactions
? semiconductor MSM5716C50/msm5718c50/md5764802 22/45 bytemask operations all memory write transactions (op1,op0 = 01) use the m7..m0 field of the req packet to control byte masking of the first octbyte dina of write data. m7 controls bits d56..d63,e7 while m0 controls bits d0..d7, e0. a 0 means dont write and a "1" means write. the m7..m0 field should be filled with 00000000 for non-memory-write transactions. op2 = 1: when op2 = 1 for a memory write transaction, the remaining data octbytes (dinb, dinc,...) are written unconditionally (all bytes are written). op2 = 0: when op2 = 0, the remaining data octbytes (dinb, dinc,...) are written with a bytemask. each bytemask is carried on the dq8 wire, pipelined one t packet interval ahead of the data octbyte it controls. figure 12 (b) shows the format of the m packet and din packet when op2 = 0. m7 controls bits d56..d63 (of the next din packet) and m0 controls bits d0..d7 (of the next din packet). figure 12 (a) summarizes the location of the m packets and the din packets they control. when 16m and 64m rdrams are used, there is no limitation caused by the use of bytemask operations; the dq8 wire is only used for the req packet and m packets. when 18m rdram is used, there is a limitation caused by the use of bytemask operations; the e7..e0 bits of the 72 bit din packet may not be used when op2 = 0. to achieve bytemasking, it will be necessary to use read-modify-write operations or single-octbyte writes with the bytemask in the req packet and op2 = 1. 8 64/72 64/72 64/72 memory data din/dout m7, m6,...m0 from req (ma) and dq8 (mb, mc,...) fig. 10 details of bytemask logic
? semiconductor MSM5716C50/msm5718c50/md5764802 23/45 fig. 11 details of bitmask logic bitmask operations all memory write transactions (op1,op0 = 01) may use bitmask operations (op5,op4). bitmask operations may be used simultaneously with the bytemask operations just described; a particular data bit is written only if the corresponding bytemask m and bitmask m are set. op5,op4 = 00: this is the default option with no bitmask operation selected; all data bits are written, subject to any bytemask operation. op5,op4 = 01: this is the write-per-bit option. figure 13 (a) shows the transaction format. the 64/ 72-bit mask register is used as a static bit mask, controlling whether each of the 64/72 bits of din octbytes is written (m = 1) or not written (m = 0). the mask register is loaded using the dynamic bitmask operation (op5,op4 = 10). op5,op4 = 10: this is the dynamic bitmask option. figure 13 (b) shows the transaction format. alternate octbytes (ma, mc,..) are loaded into the mask register to be used as a bitmask for the data octbytes (dinb, dind,...). only the col packets which correspond to din packets (colb, cold,..) contain a valid column address. the mask register is left with the last bitmask that is transferred (mc in this case). the write-enable signal is asserted after din packet (figure 11). op5,op4 = 11: this is the mask-per-bit option. figure 13 (c) shows the transaction format. the 64/ 72-bit mask register is used as a static data octbyte din. the bitmask packets (ma, mb,...) control whether the data is written (m = 1) or not written (m = 0). the mask register is loaded using the dynamic bitmask operation (op5,op4 = 10). 64/72 64/72 64/72 memory data din/dout 64/72 64/72 mask register 64/72 64/72 64/72 1 write enable (din packet) ? (op5, op4 = 10) (m packet) ? (op5, op4 = 10) op5, op4 value 01, 10 11 enable bitmask path
? semiconductor MSM5716C50/msm5718c50/md5764802 24/45 t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 clk (rx/txclk) address (busenable) command (busctrl) dq7,..dq0 (busdata[7:0]) col b col c col d wterm din a din b din c din d actv /write bnk/row /col/m a ( a ) op2 = 0 - write transaction with bytemask wstrb dq8 (busdata[8]) m b m c m d bnk/row /col fig. 12 bytemask operations m3 m2 m1 m0 d31 d23 d15 d7 d30 d22 d14 d6 d29 d21 d13 d5 d28 d20 d12 d4 d27 d19 d11 d3 d26 d18 d10 d2 d24 d16 d8 d0 d25 d17 d9 d1 dq8 dq7 dq6 dq5 dq4 dq3 dq2 dq0 dq1 clk t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 m7 m6 m5 m4 d63 d55 d47 d39 d62 d54 d46 d38 d61 d53 d45 d37 d60 d52 d44 d36 d59 d51 d43 d35 d58 d50 d42 d34 d57 d49 d41 d33 d56 d48 d40 d32 din a din b din c din d m b m c m d (b) op2 = 0 - data and bytemask packet formats
? semiconductor MSM5716C50/msm5718c50/md5764802 25/45 t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 clk (rx/txclk) address (busenable) command (busctrl) dq8,..dq0 (busdata[8:0]) col b col c col d wterm din a din b din c din d actv /write req packet bnk/row /col a (a) op5, op4 = 0, 1 - bitmask in mask register, data from dq inputs wstrb t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 clk (rx/txclk) address (busenable) command (busctrl) dq8,..dq0 (busdata[8:0]) col b col d wterm m a din b m c din d actv /write req packet bnk/row wstrb m a ( b ) op5 , op4 = 1 , 0 - bitmask from dq inputs , data from dq inputs m c mask pegister
? semiconductor MSM5716C50/msm5718c50/md5764802 26/45 t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 clk (rx/txclk) address (busenable) command (busctrl) dq8,..dq0 (busdata[8:0]) col b col c col d wterm m a m b m c m d actv /write req packet bnk/row /col a (c) op5, op4 = 1, 1 - bitmask from dq inputs, data in mask register wstrb fig. 13 bitmask operations registers there are six control registers in an rdram. they contain read-only fields, which allow a memory controller to determine the type of rdram that is present. they also contain read-write fields which are used to configure the rdram. registers are read and written with transactions that are identical to one-octbyte memory read and write transactions. these transaction formats are illustrated in figure 14. there is one difference with respect to memory transactions; for a register write, it is necessary to allow a time of t wreg to elapse before another transaction is directed to the rdram. in the descriptions of some of the read-write fields, the user is instructed to set the field to a default value (set to 1., for example). when this is done, the suggested value is the one needed for normal operation of the rdram. a summary of the control registers and a brief description follows devicetype rdram size, type information deviceid set rdram base address mode set rdram operating modes refrow set refresh address for powerdown rasinterval set ras intervals devicemfgr rdram manufacturer information the control register fields are described in detail in the next six pages. the format of the one octbyte din or dout packet that is written to or read from the register is shown. gray bits are reserved, and should be written as zero. the value of the a10..a3,regsel field needed to access each register is also shown. the row and bank address fields are not used for register read and write transactions.
? semiconductor MSM5716C50/msm5718c50/md5764802 27/45 t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 clk (rx/txclk) address (busenable) command (busctrl) dq8,..dq0 (busdata[8:0]) rreg req packet dev /col a t sdr (a) register read transaction rstrb /rterm t tdr t rsr next req dout a t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 clk (rx/txclk) address (busenable) command (busctrl) dq8,..dq0 (busdata[8:0]) din a wstrb wreg req packet dev /col a t tdw (b) register write transaction wterm t wreg t wsw next req t sdw fig. 14 register transactions
? semiconductor MSM5716C50/msm5718c50/md5764802 28/45 fig. 15 devicetype register ver3 bnk3 col3 ver2 bnk2 col2 ver1 bnk1 col1 ver0 bnk0 col0 typ3 row3 typ2 row2 bonus typ0 row0 typ1 row1 dq8 dq7 dq6 dq5 dq4 dq3 dq2 dq0 dq1 clk din/dout format description t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 devicetype register a10,a9,a8,a7,a6,a5,a4,a3,regsel 000000000 2 this is a read only register with fields that describe the characteristics of the device. this includes the number of address bits for bank, row, and column. the column count includes the (unimplemented) a2,a1,a0 bits. the other fields specify the architecture version, the device type, and the byte size. this register is read during initialization so the memory controller can determine the proper memory configuration. field 2kbyte page description ver3... ver0 0010 2 architecture version is concurrent typ3... typ0 0000 2 device is dram bnk3... bnk0 0001 2 = 1 number of bank address bits row3... row0 1001 2 = 9 number of row address bits col3... col0 1111 2 = 11 number of column address bits bonus 1 specifies 8(0) or 9(1) byte length 18m 64m 16m 0010 2 = 2 1010 2 = 10 1011 2 = 11 00
? semiconductor MSM5716C50/msm5718c50/md5764802 29/45 fig. 16 deviceid register id27 id25 id28 id24 id29 id23 id30 id22 id31 id32 id21 id34 dq8 dq7 dq6 dq5 dq4 dq3 dq2 dq0 dq1 clk din/dout format description t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 deviceid register a10,a9,a8,a7,a6,a5,a4,a3,regsel 000000001 2 this is a read-write register with a single field id35...id21. this field is compared to the a35...a21 address bits of the req packet to determine if the current transaction is directed to this rdram. if the op3 bit of the req packet is set, then this match is ignored (broadcast operation to all rdrams). note that some low order bits of this field are not compared for the higher density rdrams. field description id35..id21 compared to a35...a21 for device match id33 id35 id26 rdram size 16m/18m id35..id23 compared to a35...a23 for device match 64m
? semiconductor MSM5716C50/msm5718c50/md5764802 30/45 fig. 17 mode register c3 c5 c0 c2 c1 fr sv ft base as dq8 dq7 dq6 dq5 dq4 dq3 dq2 dq0 dq1 clk din/dout format description t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 mode register a10,a9,a8,a7,a6,a5,a4,a3,regsel 000000011 2 this is a read-write register with fields that control the operating modes of the rdram. the modes include output current control (c5..c0, ce), clock/power control (fr,ft), compatibility control (base), t tr skip control (sv, sk, as), and initialization control (de). refer to the concurrent rdram design guide for a detailed discussion of the use of these fields. field description base set to 1 if base rdrams with acknowledge are present. ccasym current control-asymmetry adjustment. sv skip value for auto t tr control. read-only. sk specifies skip value for manual t tr control. set to 0. as specifies manual (0) or auto (1) t tr control. set to 0. de device enable. used during initialization. c5... c0 specifies i ol output current. 111111 2 ? min, 000000 2 ? max. fr, ft force rxclk,txclk on. fr = 1 ? rdram enable. set ft = 0. c4 sk de ccasym
? semiconductor MSM5716C50/msm5718c50/md5764802 31/45 fig. 18 refrow register ref6 ref3 ref10 ref1 dq8 dq7 dq6 dq5 dq4 dq3 dq2 dq0 dq1 clk din/dout format description t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 refrow register a10,a9,a8,a7,a6,a5,a4,a3,regsel 000000101 2 this is a read-write register which is used to track the bank/row address that will be refreshed by the next sin pulse in powerdown mode. this register is not used for normal refresh in enable mode - the bank/row address is supplied by the external controller in the refresh transaction. powerdown is entered by setting the sp field to one. the ref field should be simultaneously set with the next bank/row to be refreshed. when powerdown is exited, this register is read from one rdram to set the proper bank/row address for normal refresh operation. the reset value of the refrow registers are all zeros. field description ref8...ref0 row address of next row to be refreshed sp set to enter powerdown mode. ref10 bank address of next row to be refreshed rdram size 16m/18m 16m/18m ref2 ref0 ref5 ref4 sp ref8 ref7 ref11 ref9 ref11, ref10 bank address of next row to be refreshed ref9...ref0 row address of next row to be refreshed 64m 64m
? semiconductor MSM5716C50/msm5718c50/md5764802 32/45 fig. 19 rasinterval register p0 p2 dq8 dq7 dq6 dq5 dq4 dq3 dq2 dq0 dq1 clk din/dout format description t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 rasinterval register a10,a9,a8,a7,a6,a5,a4,a3,regsel 000000110 2 this is a read-write register with fields that control the length of the ras intervals of the rdram. the relationship between the t rc , t rcd , t rpa and t rp intervals (in t cycle units) and the p, s, and r fields follows: t rc = (1001 2 + r + s + p) ? t cycle t rcd = (o101 2 + s) ? t cycle t rp = (o101 2 + p) ? t cycle t rpa = (o101 2 + p) ? t cycle field description s3...s0 specifies the t rcd sence interval. set to 0011 2 . p3...p0 specifies the t rp and t rpa precharge intervals. set to 0011 2 . r3...r0 specifies the (t rc - t rcd - t rp ) restore interval. set to 0111 2 . p1 p3 s0 s2 s1 s3 r0 r2 r1 r3
? semiconductor MSM5716C50/msm5718c50/md5764802 33/45 fig. 20 devicemfgr register c4 c2 dq8 dq7 dq6 dq5 dq4 dq3 dq2 dq0 dq1 clk din/dout format description t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 devicemfgr register a10,a9,a8,a7,a6,a5,a4,a3,regsel 000001001 2 this is a read-only register with fields that specify the manufacturer's identification number and manufacturer-specific date-code and version information. contact rambus for a list of manufacturer's identification numbers. field description c15...c0 manufacturer's datecode or version information m15...m0 manufacturer's identification number c3 c1 c12 c10 c11 c9 m4 m2 m3 m1 m12 m10 m11 m9 c0 c8 m0 m8 c7 c5 c6 c15 c13 c14 m7 m5 m6 m15 m13 m14
? semiconductor MSM5716C50/msm5718c50/md5764802 34/45 initialization the first step in initialization is to reset the rdram. this is accomplished by driving reset packets for a time t reset or greater. this causes the rdram to assume a known state. this also causes the internal clocking logic (a delay-locked-loop) to begin locking to the external clock. this requires a time of t lock . at this point, the rdram is ready to accept transactions. this timing sequence is shown in figure 21 (a). the next step for the memory controller is to read and write the six control registers, in order to determine the size and type of rdram that is present, and to configure it properly. a full initialization sequence is provided in the concurrent rdram design guide . power management there are several power modes available in an rdram. these modes permit power dissipation and latency to be traded against one another. enable mode: the simplest option is to remain permanently in enable power mode. this is done by setting the fr field to a one in the mode register (refer to figure 19). the rdram will return to enable mode when it is not performing a read or write transaction. this is the operating mode which has been assumed in all the transaction timing diagrams (except in figure 21 (b). suspend mode: the average power can be reduced by using suspend power mode. this is done by setting the fr field to a zero. a cke packet must be sent a time t cke ahead of each req packet (this is shown in t 0 in figure 21 (b)). this causes the rdram to transition from suspend to enable mode. when the rdram has finished the transaction, it returns to suspend mode. the average power of the rdram is reduced, but at the cost of slightly greater latency. there is no loss of effective bandwidth, since the cke packet may be overlapped with the other packet types. powerdown mode: the rdram power can be reduced to a very low level with powerdown mode. powerdown is entered by setting the sp field of the refrow register to one (the ref field is simultaneously set to the next bank and row to be refreshed). as a result, most of the rdrams circuitry is disabled, although its memory must still be refreshed. this is accomplished by pulsing the sin input with a cycle time of t scycle or less. powerdown mode is exited when pwrup packets are asserted for a time t pwrup on the command wire. the internal clocking logic will begin locking to the external clock. after a time of t lock the rdram will be in enable mode, ready for the next req packet. this is illustrated in figure 21 (c).
? semiconductor MSM5716C50/msm5718c50/md5764802 35/45 refresh memory refresh (when not in powerdown) uses a one-octbyte broadcast memory write with the following req field values: op5..0 001001 2 a35..3 dev: 0..0 (unused) auto 1 bnk: next bank actv 1 row: next row pend 000/001/010 col: 0..0 (unused) m7..0 00000000 2 regsel: 0 the transaction format for memory refresh is shown in figure 22 (a). the transaction may be noninterleaved or interleaved (if interleaved, the pend field must be properly filled). the transaction causes the requested row of the requested bank of all rdrams to be activated and then auto- precharged (note that the interval t rp + t rcd should elapse since the specified bank of some rdrams might be open). this transaction must be repeated at intervals of t ref / (n bnk ?n row ), where n bnk and n row are the number of banks and rows in the rdram. this interval will be the same for the different rdram configurations. for each refresh transaction, the bank and row field of a35..a3 must be incremented, with the bank field changing most often so the t ras, max parameter is not exceeded. current control the transaction format for current control is shown in figure 22 (b). this transaction is encoded as a directed register read operations, and is repeated at intervals of t cctrl /n dev , where n dev is the number of devices on the channel. this will maintain the optimal current control value. op5..0 000110 2 a35..3 dev: next device auto 0 bnk: 0..0 (unused) actv 0 row: 0..0 (unused) pend 000 col: 00000101 2 m7..0 00000000 2 regsel: 0 after a t lock , a series of 64 of these current control transactions must be directed to each device on the channel to establish the optimal current control value.
? semiconductor MSM5716C50/msm5718c50/md5764802 36/45 fig. 21 transactions using reset, cke, and pwrup packets t 10 t 9 t 8 t 7 ? ? ? t 5 t 4 t 3 ? ? ? t 1 t 0 clk (rx/txclk) address (busenable) command (busctrl) dq8,..dq0 (busdata[8:0]) (a) reset packet for initialization reset t reset reset reset req packet bnk/row /col a t lock ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? t 10 t 9 t 8 t 7 ? ? ? t 5 t 4 t 3 ? ? ? t 1 t 0 clk (rx/txclk) address (busenable) command (busctrl) dq8,..dq0 (busdata[8:0]) (c) pwrup packet for powerdown-to-enable power mode transition pwrup t pwrup pwrup req packet bnk/row /col a t lock ? ? ? ? ? ? ? ? ? t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 clk (rx/txclk) address (busenable) command (busctrl) dq8,..dq0 (busdata[8:0]) (b) cke packet for suspend-to-enable power mode transition t cke cke req packet bnk/row /col a1 ? ? ? ? ? ? ? ? ?
? semiconductor MSM5716C50/msm5718c50/md5764802 37/45 t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 clk (rx/txclk) address (busenable) command (busctrl) dq8,..dq0 (busdata[8:0]) wstrb actv /writea req packet bnk/row t rp + t rcd t cac next req wstrb actv /writea req packet bnk/row t rp + t rcd t cac next req t ref / (n bnk ? n row ) ? ? ? ? ? ? ? ? ? (a) refresh transaction clk (rx/txclk) address (busenable) command (busctrl) dq8,..dq0 (busdata[8:0]) rreg req packet dev /col a next req t cctrl /n dev ? ? ? ? ? ? ? ? ? ( b ) current control transaction rreg req packet dev /col a wterm din a wterm din a dout b dout a dout a ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rterm rstrb rstrb rterm *** fig. 22 refresh and current control transactions due to the nature of the current control operation, a delay of 4 busclks may be needed before and after the current control transaction. if the request immediately before the current control request is a write request, there should be a 4 busclks (1 synclk) delay between the end of write data and the beginning of the rdram current control request (see * in figure 22 (b)). if the request immediately before the current control request is a read request, no delay is required. if the current control data is followed by a request using the mode register address, there must be a 4busclks (1 synclk) delay between the end of current control data transport and the subsequent requests using the mode register addresses (see ** in figure 22 (b)). any other request may immediately follow the currrent control data transport.
? semiconductor MSM5716C50/msm5718c50/md5764802 38/45 absolute maximum ratings the following table represents stress ratings only, and functional operation at the maximum ratings is not guaranteed. extended exposure to the maximum ratings may affect device reliability. although these devices contain protective circuitry to resist damage from static electric discharge, always take precautions to avoid high static voltages or electric fields. v i,abs v dd,max +0.3 symbol parameter unit voltage applied to any rsl pin with respect to gnd max. min. C0.3 v v i,cmos,abs v dd +0.3 voltage applied to any cmos pin with respect to gnd C0.3 v v dd,abs v dd,max +1.0 voltage on v dd with respect to gnd C0.3 v t j,abs 125 junction temperature under bias C55 c t store 125 storage temperature C55 c thermal parameters t j 100 symbol parameter and conditions unit junction operating temperature max. min. 0c q jc 5 junction-to-case thermal resistance c/watt c i 2.0 a /2.5 b symbol parameter and conditions unit rsl input parasitic capacitance max. min. 1.6 a /2.0 b pf c i,cmos 8 cmos input parasitic capacitance pf l i 2.7 a /5.0 b rsl input parasitic inductance nh powerdown 1.0 mode description unit device shut down, clock unlocked max. min. ma suspend 95 device inactive, clock locked but suspended ma actv/read 600 device reading column data in bank 1 and activating row in bank 2 ma actv/write 580 device writing column data in bank 1 and activating row in bank 2 ma enable 340 device active, clock unlocked and enabled ma read 500 device reading column data ma write 430 device writing column data ma (ta = 0?c to 70?c) actv/enable 330 device evaluating req packet and activating row in bank ma capacitance notes: a. 16m/18m rdram. b. 64m rdram. idd-supply current profile
? semiconductor MSM5716C50/msm5718c50/md5764802 39/45 recommended electrical conditions v dd, v dda 3.45 symbol parameter and conditions unit supply voltage 3.3 v version max. min. 3.15 v v ref v dd C0.8 reference voltage 1.9 v v il v ref C0.8 rsl input low voltage b v ref C0.35 v v ih v ref +0.8 rsl input high voltage b v ref +0.35 v v il,cmos 0.8 cmos input low voltage C0.5 v v ih,cmos v dd +0.5 cmos input high voltage 1.8 v (ta = 0?c to 70?c) electrical characteristics i ref 10 symbol parameter and conditions unit v ref current @ v ref,max max. min. C10 m a i oh 10 rsl output high current @ (0 v out v dd ) C10 m a i none (manual) 4.0 rsl i ol current @ v out = 1.6 v @ c[5:0] = 000000 (0 10 ) a 0.0 ma i all (manual) 80.0 rsl i ol current @ v out = 1.6 v @ c[5:0] = 111111 (63 10 ) a 30.0 ma i i,cmos 10.0 cmos input leakage current @ (0 v i,cmos v dd ) C10.0 m a v ol,cmos 0.4 cmos output voltage @ i ol,cmos = 1.0 ma 0.0 v v oh,cmos v dd cmos output high voltage @ i oh,cmos = C0.25 ma 2.0 v (ta = 0?c to 70?c) note: a. in manual-calibration mode (ccenable = 0) this is the value written into the c[5:0] field of the mode register to produce the indicated i ol value. values of i ol in between the i none and i all are produced by interpolating c[5:0] to intermediate values. for example, c[5:0] = 011111 (31 10 ) produces an i ol in the range of 20 to 40 ma. b. i ol of bus data outputs is set at 30 ma when bus enable pin v ih /v il value is measured.
? semiconductor MSM5716C50/msm5718c50/md5764802 40/45 recommended timing conditions t cr , t cf 0.8 symbol parameter unit txclk and rxclk input rise and fall times max. min. 0.3 ns t cycle 4.15 a / 4.15 b txclk and rxclk cycle times 3.75 a / 3.33 b ns transfer time per bit per pin (this timing interval is synthesized by the rdram ' s clock generator) 0.5 0.5 t tick t cycle t ch , t cl 55% txclk and rxclk high and low times 45% t cycle t tr 0.7 txclk-rxclk differential 0 t cycle t dr , t df 0.6 dq/address/command input rise and fall times 0.3 ns t s dq/address/command-to-rxclk setup time 0.35 c ns t h rxclk-to-dq/address/command hold time 0.35 c ns t ref 17 d / 33 e refresh interval ms t scycle 16.6 d / 8.0 e powerdown refresh cycle time 0.4 m s t sl 10 powerdown refresh low time 0.2 m s t sh 10 powerdown refresh high time 0.2 m s t cctrl 150 current control interval ms t ras 133 ras interval (time a row may stay activated) m s t lock 5.0 rdram clock-locking time for reset or powerup m s t packet 4 transfer time for req, din, dout, col, wstrb, wterm, rstrb, rterm, cke, pwrup and reset packets 4t cycle (ta = 0?c to 70?c) notes: a. 533 mhz rdram b. 600 mhz rdram c. 600 mhz io timing d. 16m/18mbit e. 64mbit
? semiconductor MSM5716C50/msm5718c50/md5764802 41/45 timing characteristics note: a. 600 mhz io timing rambus channel timing the next table shows important timings on the rambus channel for common operations. all timings are from the point of view of the channel master, and thus have the bus overhead delay of t cycle per bus transversal included where appropriate. t pio 25 symbol parameter unit sin-to-sout delay @ c load,cmos = 40 pf max. min. 1ns t q dq output time ns (ta = 0?c to 70?c) t qr, t qf 0.5 dq output rise and fall times 0.3 ns 0.4 a C0.4 a symbol and figure parameter min. max. t cac - figure 8,9 column access time. may overlap t rcd , t rp , or t rpa to another bank 6 a / 7 b t cc - figure 8,9 column cycle time. may overlap t rcd , t rp , or t rpa to another bank 4 t rcd - figure 8,9 row to column delay. may overlap t cac or t cc to another bank 8 t rp - figure 8,9 row precharge time. may overlap t cac or t cc to another bank 8 t rpa - figure 8,9 row precharge auto. may overlap t rpa , t cac or t cc to another bank 8 t rac - figure 8,9 row access time. (t rac = t rcd + t cac ). 15 t rc - figure 8,9 row cycle time. (t rc = t rp + t rcd + t cac ). 23 t rsr - figure 8 (a) start of req (read) to start of rstrb packet for read transaction. 2 t asr - figure 8 (b) start of req (actv/read) to start of rstrb packet for read transaction. 11 t psr - figure 8 (c) start of req (pre/actv/read) to start of rstrb packet for read transaction. 19 t cdr - figure 8 start of col packet to start of dout packet for read transaction. 12 12 t sdr - figure 8 88 t tdr - figure 8 12 12 start of rstrb packet to start of dout packet for read transaction. start of rterm packet to end of dout packet for read transaction. t wsw - figure 9 (a) start of req (write) to start of wstrb packet for write transaction. 0 t asw - figure 9 (b) start of req (actv/write) to start of wstrb packet for write transaction. 5 t psw - figure 9 (c) start of req (pre/actv/write) to start of wstrb packet for write transaction. 13 t cdw - figure 9 start of col packet to start of din packet for write transaction. 8 8 t sdw - figure 9 44 t tdw - figure 9 44 start of wstrb packet to start of din packet for write transaction. start of wterm packet to end of din packet for write transaction. t reset - figure 21 (a) length of reset packets to cause rdram to reset. 800 ns t cke - figure 21 (b) start of cke packet to start of req packet for suspend-to-enable. 47 t pwrup - figure 21 (c) 88 t wreg - figure 14 (b) 16 length of pwrup packets to cause powerdown-to-enable. end of din packet for wreg transaction to start of next req packet. note: all units are t cycle when not mentioned a. for read, write commands b. for actv/read, actv/write, pre/actv/read, pre/actv/write commands (ta = 0?c to 70?c)
? semiconductor MSM5716C50/msm5718c50/md5764802 42/45 timing waveform rsl rise/fall timing v rxclk v txclk 80% v ih,min 20% v il,max t cf t cr v dq,in v command 80% v ih,min 20% v il,max t df t dr v address v dq,out 80% v oh,min 20% v ol,max t qf t qr where: v oh,min = v term,min v ol,max = v term,max - z o * (i ol,min ) rsl clock timing v txclk logic 0, v ih v ref logic 1, v il t tr logic 0, v ih v ref logic 1, v il v rxclk t cl t ch t cycle t cycle t cl t ch
? semiconductor MSM5716C50/msm5718c50/md5764802 43/45 rsl input (receive) timing logic 0, v ih v ref logic 1, v il v rxclk t cycle t tick (even) t tick (odd) logic 0, v ih v ref logic 1, v il t s t h t s t h v command v address rsl output (transmit) timing logic 0, v oh 50% logic 1, v ol v txclk t cycle t tick (even) t tick (odd) logic 0, v oh 50% logic 1, v ol t q,max t q,max t q,min v dq,out t q,min t cycle /4 t cycle /4
? semiconductor MSM5716C50/msm5718c50/md5764802 44/45 sin/sout timing logic 1 v sw,cmos logic 0 logic 1 v sw,cmos logic 0 logic 1 v sw,cmos logic 0 v sin v sout v sin t pio,max t pio,min t sl t sh t scycle v sw,cmos = 1.5 v
? semiconductor MSM5716C50/msm5718c50/md5764802 45/45 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). shp32-p-1125-0.65-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more typ. mirror finish

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